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[RISCV] Incorrect definition of InsnCI #100112

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svs-quic opened this issue Jul 23, 2024 · 1 comment · Fixed by #100113
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[RISCV] Incorrect definition of InsnCI #100112

svs-quic opened this issue Jul 23, 2024 · 1 comment · Fixed by #100113
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backend:RISC-V

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@svs-quic
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According to the spec:

26.2. Compressed Instruction Formats
CR, CI, and CSS can use any of the 32 RVI registers, but CIW, CL, CS, CA, and CB are limited to just 8 of them.

But the definition in RISCVInstrInfoC.td has it taking AnyRegC. This should be AnyReg.

def InsnCI : DirectiveInsnCI<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode,
@svs-quic svs-quic mentioned this issue Jul 23, 2024
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@llvmbot
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llvmbot commented Jul 23, 2024

@llvm/issue-subscribers-backend-risc-v

Author: Sudharsan Veeravalli (svs-quic)

According to the spec:

> 26.2. Compressed Instruction Formats
> CR, CI, and CSS can use any of the 32 RVI registers, but CIW, CL, CS, CA, and CB are limited to just 8 of them.

But the definition in RISCVInstrInfoC.td has it taking AnyRegC. This should be AnyReg.

def InsnCI : DirectiveInsnCI&lt;(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode,

sgundapa pushed a commit to sgundapa/upstream_effort that referenced this issue Jul 23, 2024
@svs-quic @sgundapa
[RISCV] Fix InsnCI register type (llvm#100113)
53742f5 
According to the spec the CI type instructions can take any of the 32
RVI registers.

Fixes llvm#100112
llvmbot pushed a commit to llvmbot/llvm-project that referenced this issue Jul 24, 2024
@svs-quic @llvmbot
[RISCV] Fix InsnCI register type (llvm#100113)
fe48a71 
According to the spec the CI type instructions can take any of the 32
RVI registers.

Fixes llvm#100112

(cherry picked from commit 1ebfc81)
lenary pushed a commit to llvmbot/llvm-project that referenced this issue Jul 24, 2024
@svs-quic @lenary
[RISCV] Fix InsnCI register type (llvm#100113)
f9d32a6 
According to the spec the CI type instructions can take any of the 32
RVI registers.

Fixes llvm#100112

(cherry picked from commit 1ebfc81)
tru pushed a commit to llvmbot/llvm-project that referenced this issue Jul 24, 2024
@svs-quic @tru
[RISCV] Fix InsnCI register type (llvm#100113)
411bb69 
According to the spec the CI type instructions can take any of the 32
RVI registers.

Fixes llvm#100112

(cherry picked from commit 1ebfc81)
yuxuanchen1997 pushed a commit that referenced this issue Jul 25, 2024
@svs-quic @yuxuanchen1997
[RISCV] Fix InsnCI register type (#100113)
9881959 
Summary:
According to the spec the CI type instructions can take any of the 32
RVI registers.

Fixes #100112

Test Plan: 

Reviewers: 

Subscribers: 

Tasks: 

Tags: 


Differential Revision: https://phabricator.intern.facebook.com/D60251158
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[RISCV] Fix InsnCI register type svs-quic/llvm-project
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