If you do not have a Cadence Allegro Schematics, you can still use IBERTpy but you need to generate yourself the connectivity CSV files.
- Connectivity CSV files (in/csv) generated by PCBpy for Cadence Allegro PCB projects https://github.com/mvsoliveira/PCBpy
- TCL (in/tcl) and LaTeX (in/tex) template files
After Step 2 (ibert_tcl_tex_generator.py):
- TCL (out/tcl) files to configure IBERT links connectivity, polarity and run settings
- TEX files to compile all the eye diagrams in a single PDF
After steps 6:
- PDF (out/pdf) files with summary scatter plots of eye openning (generate_all_hists.py)
- PDF (scans/pdf) files with eye diagrams for every link in different configurations (generate_all_plots.py)
After step 7:
- PDF Report with all the eye diagrams (latex/report.tex). Example here.
- Generate board netlist files using PCBpy. See instructions here.
- Get FPGA package files here.
PCBpy reads only the Xilinx CSV files at the moment.
A) Edit the ibert_tcl_tex_generator.py with the following information:
- csvfiles: Relative files to CSV package files
- schem_map: Dictionary of schematics reference designators to ibert instance and device name for the report
- runs: Array of dictionaries listing the connectivity of each of the testing runs. Multiple runs are needed when all the inputs/outpus can't be connected simmultaneously.
- tex_runs: Names for different set of runs. Used to distinguish in the report results from different data rates or different board versions.
- link_tex_templates: Make sure a LaTeX template exists for all the summary pages you need.
- Make sure in/tcl/SetIBERTRunTemplate.tcl contains the call for each of the tcl files carrying the link settings. Examples are: polarities, power-down, PRBS mode, swing, enphasis and others. The transceiver polarirty tcl scripts are automatically generated by PCBpy.
B) Run ibert_tcl_tex_generator.py and check the results at out/tcl and out/tex
IBERTpy checks if each of the scan csv files exist before generating the TeX files in order to avoid latex compiling errors.
Therefore, after finishing all the scans, run ibert_tcl_tex_generator.py again to double check if any scan csv is missing.
The following message is shown in case of missing scan csv files:
Skipping MSP_C_FPGA-IC39-00--IC15-00-TRP_FPGA because the file ../scans/csv/V3-12.8/MSP_C_FPGA-IC39-00--IC15-00-TRP_FPGA.csv was not found
- Configure the board
- Open the Vivado Hardware Manager
- Connect to the board
- Make sure the TCL console is in the folder at which the out/tcl scripts are
- Run the SetIBERT Run?.tcl corresponding to the run you are insterested to
- Check the link settings and status
- Make sure ../scans/csv/ path exists
- Change run settings at scan.tcl file if needed
- Run ScanRun ?.tcl
- Wait until all the scans are finished, the scan files are placed at ../scans/csv/
- Organize the CSV scan files into a different folder for each of the different tex_runs listed in step 2.4
- Make sure that the same folders exist at scans/pdf/
- Make sure matplitlib is installed in your python envinronment
- Run generate_all_plots.py to generate a PDF file for each CSV file
- Run generate_all_hists.py to generate summary histograms
Make sure rates is set according to tex_runs defined in step 2.4.
The variable link_set is set to filter the CSV files of interest.
The main LaTeX report.tex file is not generated automatically yet. However, all the summary and detailed pages are automatically generated.
One can run LaTeX in the cloud, using services such as overleaf.com or locally using a LaTeX distribution of preference.
Popular distributions are TeX Live (http://tug.org/texlive/) and MiKTeX (https://miktex.org/).
- Edit the report.tex main TeX file accordingly. The output from genTexInputCalls(tex_files) method in ibert_tcl_tex_generator.py can be useful.
- Make sure you LaTeX environment includes the packages used in the report.tex file
- Compile the LaTex report file. You should expect to get a Table of Contents with entries for each summary and detailed pages.