Merge pull request #2 from forg0ne/release/v1.32.01

Release/v1.32.01
weston-embedded · May 4, 2021 · fe140a6 · fe140a6
2 parents d963fd3 + 29e9b20
commit fe140a6
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Showing 208 changed files with 476 additions and 583 deletions.
diff --git a/78K0/IAR/cpu.h b/78K0/IAR/cpu.h
@@ -3,7 +3,7 @@
 *                                               uC/CPU
 *                                    CPU CONFIGURATION & PORT LAYER
 *
-*                    Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+*                    Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 *
 *                                 SPDX-License-Identifier: APACHE-2.0
 *
@@ -23,7 +23,7 @@
 *                                IAR C/C++ Compiler for NEC 78K0 4.60A
 *
 * Filename : cpu.h
-* Version  : v1.32.00
+* Version  : V1.32.01
 *********************************************************************************************************
 */
 
@@ -476,4 +476,3 @@ void    CPU_SR_Restore(CPU_SR  cpu_sr);
 */
 
 #endif                                                          /* End of CPU module include.                           */
-
diff --git a/78K0R/IAR/cpu.h b/78K0R/IAR/cpu.h
@@ -3,7 +3,7 @@
 *                                               uC/CPU
 *                                    CPU CONFIGURATION & PORT LAYER
 *
-*                    Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+*                    Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 *
 *                                 SPDX-License-Identifier: APACHE-2.0
 *
@@ -23,7 +23,7 @@
 *                                IAR C/C++ Compiler for NEC 78K0R 4.60A
 *
 * Filename : cpu.h
-* Version  : v1.32.00
+* Version  : V1.32.01
 *********************************************************************************************************
 */
 
@@ -476,4 +476,3 @@ void    CPU_SR_Restore(CPU_SR  cpu_sr);
 */
 
 #endif                                                          /* End of CPU module include.                           */
-
diff --git a/ARC/EM6/MetaWare/cpu.h b/ARC/EM6/MetaWare/cpu.h
@@ -3,7 +3,7 @@
 *                                               uC/CPU
 *                                    CPU CONFIGURATION & PORT LAYER
 *
-*                    Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+*                    Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 *
 *                                 SPDX-License-Identifier: APACHE-2.0
 *
@@ -24,7 +24,7 @@
 *
 *
 * Filename : cpu.h
-* Version  : v1.32.00
+* Version  : V1.32.01
 *********************************************************************************************************
 */
 
@@ -604,4 +604,3 @@ void      CPU_SR_Restore     (CPU_SR          cpu_sr);          /* Restore CPU s
 #endif
 
 #endif                                                          /* End of CPU module include.                           */
-
diff --git a/ARC/EM6/MetaWare/cpu_a.s b/ARC/EM6/MetaWare/cpu_a.s
@@ -2,7 +2,7 @@
 ;                                               uC/CPU
 ;                                   CPU CONFIGURATION & PORT LAYER
 ;
-;                   Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+;                   Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 ;
 ;                                SPDX-License-Identifier: APACHE-2.0
 ;
@@ -21,7 +21,7 @@
 ;
 ;
 ; Filename : cpu_a.s
-; Version  : v1.32.00
+; Version  : V1.32.01
 ;********************************************************************************************************
 
 
@@ -256,4 +256,3 @@ FUNCTION CPU_TS_TmrRd
 ;********************************************************************************************************
 
 .end
-
diff --git a/ARC/EM6/MetaWare/cpu_c.c b/ARC/EM6/MetaWare/cpu_c.c
@@ -3,7 +3,7 @@
 *                                               uC/CPU
 *                                    CPU CONFIGURATION & PORT LAYER
 *
-*                    Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+*                    Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 *
 *                                 SPDX-License-Identifier: APACHE-2.0
 *
@@ -24,7 +24,7 @@
 *
 *
 * Filename : cpu_c.c
-* Version  : v1.32.00
+* Version  : V1.32.01
 *********************************************************************************************************
 */
 

diff --git a/ARM-Cortex-A/ARMv7-A/ARM/cpu.h b/ARM-Cortex-A/ARMv7-A/ARM/cpu.h
@@ -3,7 +3,7 @@
 *                                               uC/CPU
 *                                    CPU CONFIGURATION & PORT LAYER
 *
-*                    Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+*                    Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 *
 *                                 SPDX-License-Identifier: APACHE-2.0
 *
@@ -23,7 +23,7 @@
 *                                           ARM C Compiler
 *
 * Filename : cpu.h
-* Version  : v1.32.00
+* Version  : V1.32.01
 *********************************************************************************************************
 */
 
@@ -535,4 +535,3 @@ void        CPU_WaitForEvent (void);
 #endif
 
 #endif                                                          /* End of CPU module include.                           */
-
diff --git a/ARM-Cortex-A/ARMv7-A/ARM/cpu_a.s b/ARM-Cortex-A/ARMv7-A/ARM/cpu_a.s
@@ -2,7 +2,7 @@
 ;                                               uC/CPU
 ;                                    CPU CONFIGURATION & PORT LAYER
 ;
-;                    Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+;                    Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 ;
 ;                                 SPDX-License-Identifier: APACHE-2.0
 ;
@@ -20,7 +20,7 @@
 ;                                           ARM C Compiler
 ;
 ; Filename : cpu_a.s
-; Version  : v1.32.00
+; Version  : V1.32.01
 ;********************************************************************************************************
 
 
@@ -254,4 +254,3 @@ CPU_CntTrailZeros FUNCTION
 ;********************************************************************************************************
 
         END
-
diff --git a/ARM-Cortex-A/ARMv7-A/CCS/cpu.h b/ARM-Cortex-A/ARMv7-A/CCS/cpu.h
@@ -3,7 +3,7 @@
 *                                               uC/CPU
 *                                    CPU CONFIGURATION & PORT LAYER
 *
-*                    Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+*                    Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 *
 *                                 SPDX-License-Identifier: APACHE-2.0
 *
@@ -23,7 +23,7 @@
 *                                            TI C Compiler
 *
 * Filename : cpu.h
-* Version  : v1.32.00
+* Version  : V1.32.01
 *********************************************************************************************************
 */
 
@@ -501,4 +501,3 @@ void        CPU_WaitForEvent (void);
 #endif
 
 #endif                                                          /* End of CPU module include.                           */
-
diff --git a/ARM-Cortex-A/ARMv7-A/CCS/cpu_a.asm b/ARM-Cortex-A/ARMv7-A/CCS/cpu_a.asm
@@ -2,7 +2,7 @@
 ;                                               uC/CPU
 ;                                    CPU CONFIGURATION & PORT LAYER
 ;
-;                    Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+;                    Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 ;
 ;                                 SPDX-License-Identifier: APACHE-2.0
 ;
@@ -20,7 +20,7 @@
 ;                                            TI C Compiler
 ;
 ; Filename : cpu_a.asm
-; Version  : v1.32.00
+; Version  : V1.32.01
 ;********************************************************************************************************
 
      .text
@@ -219,4 +219,3 @@ CPU_CntTrailZeros:
         RBIT    R0, R0                          ; Reverse bits
         CLZ     R0, R0                          ; Count trailing zeros
         BX      LR
-
diff --git a/ARM-Cortex-A/ARMv7-A/GNU/cpu.h b/ARM-Cortex-A/ARMv7-A/GNU/cpu.h
@@ -3,7 +3,7 @@
 *                                               uC/CPU
 *                                    CPU CONFIGURATION & PORT LAYER
 *
-*                    Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+*                    Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 *
 *                                 SPDX-License-Identifier: APACHE-2.0
 *
@@ -23,7 +23,7 @@
 *                                           GNU C Compiler
 *
 * Filename : cpu.h
-* Version  : v1.32.00
+* Version  : V1.32.01
 *********************************************************************************************************
 */
 
@@ -503,4 +503,3 @@ void        CPU_WaitForEvent (void);
 #endif
 
 #endif                                                          /* End of CPU module include.                           */
-
diff --git a/ARM-Cortex-A/ARMv7-A/GNU/cpu_a.S b/ARM-Cortex-A/ARMv7-A/GNU/cpu_a.S
@@ -2,7 +2,7 @@
 @                                               uC/CPU
 @                                    CPU CONFIGURATION & PORT LAYER
 @
-@                    Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+@                    Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 @
 @                                 SPDX-License-Identifier: APACHE-2.0
 @
@@ -20,7 +20,7 @@
 @                                           GNU C Compiler
 @
 @ Filename : cpu_a.S
-@ Version  : v1.32.00
+@ Version  : V1.32.01
 @********************************************************************************************************
 
 
@@ -220,4 +220,3 @@ CPU_CntTrailZeros:
 @********************************************************************************************************
 
     .end
-
diff --git a/ARM-Cortex-A/ARMv7-A/IAR/cpu.h b/ARM-Cortex-A/ARMv7-A/IAR/cpu.h
@@ -3,7 +3,7 @@
 *                                               uC/CPU
 *                                    CPU CONFIGURATION & PORT LAYER
 *
-*                    Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+*                    Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 *
 *                                 SPDX-License-Identifier: APACHE-2.0
 *
@@ -23,7 +23,7 @@
 *                                              IAR EWARM
 *
 * Filename : cpu.h
-* Version  : v1.32.00
+* Version  : V1.32.01
 *********************************************************************************************************
 */
 
@@ -511,4 +511,3 @@ void        CPU_WaitForEvent (void);
 #endif
 
 #endif                                                          /* End of CPU module include.                           */
-
diff --git a/ARM-Cortex-A/ARMv7-A/IAR/cpu_a.asm b/ARM-Cortex-A/ARMv7-A/IAR/cpu_a.asm
@@ -2,7 +2,7 @@
 ;                                               uC/CPU
 ;                                    CPU CONFIGURATION & PORT LAYER
 ;
-;                    Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+;                    Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 ;
 ;                                 SPDX-License-Identifier: APACHE-2.0
 ;
@@ -20,7 +20,7 @@
 ;                                              IAR EWARM
 ;
 ; Filename : cpu_a.asm
-; Version  : v1.32.00
+; Version  : V1.32.01
 ;********************************************************************************************************
 
 
@@ -214,4 +214,3 @@ CPU_CntTrailZeros
 ;********************************************************************************************************
 
     END
-
diff --git a/ARM-Cortex-A/ARMv8-A/ARM/cpu.h b/ARM-Cortex-A/ARMv8-A/ARM/cpu.h
@@ -3,7 +3,7 @@
 *                                               uC/CPU
 *                                    CPU CONFIGURATION & PORT LAYER
 *
-*                    Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+*                    Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 *
 *                                 SPDX-License-Identifier: APACHE-2.0
 *
@@ -23,7 +23,7 @@
 *                                           ARM C Compiler
 *
 * Filename : cpu.h
-* Version  : v1.32.00
+* Version  : V1.32.01
 *********************************************************************************************************
 */
 
@@ -527,4 +527,3 @@ void        CPU_WaitForEvent (void);
 #endif
 
 #endif                                                          /* End of CPU module include.                           */
-
diff --git a/ARM-Cortex-A/ARMv8-A/ARM/cpu_a.s b/ARM-Cortex-A/ARMv8-A/ARM/cpu_a.s
@@ -2,7 +2,7 @@
 ;                                               uC/CPU
 ;                                    CPU CONFIGURATION & PORT LAYER
 ;
-;                    Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+;                    Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 ;
 ;                                 SPDX-License-Identifier: APACHE-2.0
 ;
@@ -20,7 +20,7 @@
 ;                                           ARM C Compiler
 ;
 ; Filename : cpu_a.s
-; Version  : v1.32.00
+; Version  : V1.32.01
 ;********************************************************************************************************
 
 
@@ -259,4 +259,3 @@ CPU_CntTrailZeros FUNCTION
 ;********************************************************************************************************
 
         END
-
diff --git a/ARM-Cortex-A/ARMv8-A/GNU/cpu.h b/ARM-Cortex-A/ARMv8-A/GNU/cpu.h
@@ -3,7 +3,7 @@
 *                                               uC/CPU
 *                                    CPU CONFIGURATION & PORT LAYER
 *
-*                    Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+*                    Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 *
 *                                 SPDX-License-Identifier: APACHE-2.0
 *
@@ -23,7 +23,7 @@
 *                                           GNU C Compiler
 *
 * Filename : cpu.h
-* Version  : v1.32.00
+* Version  : V1.32.01
 *********************************************************************************************************
 */
 
@@ -540,4 +540,3 @@ void        CPU_WaitForEvent (void);
 #endif
 
 #endif                                                          /* End of CPU module include.                           */
-
diff --git a/ARM-Cortex-A/ARMv8-A/GNU/cpu_a.S b/ARM-Cortex-A/ARMv8-A/GNU/cpu_a.S
@@ -3,7 +3,7 @@
 *                                               uC/CPU
 *                                    CPU CONFIGURATION & PORT LAYER
 *
-*                    Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
+*                    Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
 *
 *                                 SPDX-License-Identifier: APACHE-2.0
 *
@@ -23,7 +23,7 @@
 *                                           GNU C Compiler
 *
 * Filename : cpu_a.S
-* Version  : v1.32.00
+* Version  : V1.32.01
 *********************************************************************************************************
 */