Merge branch 'add-immediate-op-size' into 'main'

Add size top op_immediate and change size of op_indirect to bytes

See merge request rewriting/ddisasm!1182

src/datalog/arch/arch.dl

@@ -215,7 +215,7 @@ Dst may be an untracked register.
 move_reg_imm(EA,Dst,Value,1):-
     instruction(EA,_,_,Operation,Op1,Op2,0,0,_,_),
     move_operation(Operation),
-    op_immediate(Op1,Value),
+    op_immediate(Op1,Value,_),
     op_regdirect_contains_reg(Op2,Dst).
 
 .decl move(EA:address)
@@ -531,9 +531,9 @@ instruction_at(Instruction,Instruction):-
     instruction(Instruction,_,_,_,_,_,_,_,_,_).
 
 /**
-The size of a register, in bits.
+The size of a register, in bytes.
 */
-.decl register_size_bits(Reg:input_reg,Size:unsigned)
+.decl register_size_bytes(Reg:input_reg,Size:unsigned)
 
 // ===========================================================================
 // Other architectural attributes

src/datalog/arch/arm32/arch_arm.dl

@@ -165,7 +165,7 @@ pc_relative_disp(EA,Disp):-
 pc_relative_addr(EA,Reg,Val):-
     instruction(EA,_,_,Operation,OffsetOp,DestOp,0,_,_,_),
     substr(Operation,0,3) = "ADR",
-    op_immediate(OffsetOp, Offset),
+    op_immediate(OffsetOp, Offset,_),
     op_regdirect_contains_reg(DestOp,Reg),
     pc_relative_disp(EA,Disp),
     Val = as(as(EA - (EA band 3),number) + Offset + Disp,address).
@@ -177,7 +177,7 @@ pc_relative_addr(EA,Reg,Val):-
         ;
         substr(Operation,0,3) = "SUB", Sign = -1
     ),
-    op_immediate(OffsetOp, Offset),
+    op_immediate(OffsetOp, Offset,_),
     op_regdirect_contains_reg(DestOp,Reg),
     op_regdirect_contains_reg(PCOp,PC),
     arch.pc_reg(PC),
@@ -411,7 +411,7 @@ reg_imm_bitwise_binary_op(EA,DstReg,SrcReg,Imm,Op):-
     ),
     op_regdirect_contains_reg(DstRegOp,DstReg),
     op_regdirect_contains_reg(SrcRegOp,SrcReg),
-    op_immediate(ImmOp,Imm).
+    op_immediate(ImmOp,Imm,_).
 
 reg_reg_bitwise_binary_op(EA,DstReg,SrcReg1,SrcReg2,Op):-
     instruction(EA,_,_,Operation,SrcRegOp,DstRegOp,0,0,_,_),
@@ -449,7 +449,7 @@ reg_arithmetic_operation(EA,Reg,Reg,1,Sign*Immediate):-
         Operation = "ADD", Sign = 1;
         Operation = "SUB", Sign = -1
     ),
-    op_immediate(Op1,Immediate),
+    op_immediate(Op1,Immediate,_),
     op_regdirect_contains_reg(Op2,Reg).
 
 // ADD/SUB reg, reg, #imm
@@ -460,15 +460,15 @@ reg_arithmetic_operation(EA,Dst,Src,1,Sign*Immediate):-
         Operation = "SUB", Sign = -1
     ),
     op_regdirect_contains_reg(Op1,Src),
-    op_immediate(Op2,Immediate),
+    op_immediate(Op2,Immediate,_),
     op_regdirect_contains_reg(Op3,Dst).
 
 // ADD Reg1, Reg2, N, M
 reg_arithmetic_operation(EA,DstReg,Reg,1,Val):-
     instruction(EA,_,_,"ADD",Op1,Op2,Op3,DstOp,_,_),
     op_regdirect_contains_reg(Op1,Reg),
-    op_immediate(Op2,N),
-    op_immediate(Op3,M),
+    op_immediate(Op2,N,_),
+    op_immediate(Op3,M,_),
     op_regdirect_contains_reg(DstOp,DstReg),
     N >= 0,
     // N right-rotate M

src/datalog/arch/arm32/memory_access.dl

@@ -192,7 +192,7 @@ reg_arithmetic_operation(EA,Rn_nn,Rn_nn,1,Offset):-
     op_indirect_mapped(Op1,_,Rn,"NONE",_,0,_),
     !non_mult_shift(EA,Op1),
     reg_nonnull(Rn,Rn_nn),
-    op_immediate(Op2,Offset).
+    op_immediate(Op2,Offset,_).
 
 // Post-index register (3)
 memory_access(AccessType,EA,SrcIdx,DstIdx,Rt,Rn,"NONE",0,0),
@@ -244,7 +244,7 @@ reg_arithmetic_operation(EA,Rn_nn,Rn_nn,1,Offset):-
     op_indirect_mapped(Op2,_,Rn,"NONE",_,0,_),
     !non_mult_shift(EA,Op2),
     reg_nonnull(Rn,Rn_nn),
-    op_immediate(Op3,Offset).
+    op_immediate(Op3,Offset,_).
 
 // Post-index register (6)
 memory_access(AccessType,EA,SrcIdx1,DstIdx1,Rt,Rn,"NONE",0,0),

src/datalog/arch/arm32/registers.dl

@@ -66,7 +66,7 @@ general_purpose_reg("SP").
 general_purpose_reg("LR").
 general_purpose_reg("PC").
 
-register_size_bits(InputReg,32):-
+register_size_bytes(InputReg,4):-
     general_purpose_reg(Reg),
     reg_map(InputReg,Reg).
 

src/datalog/arch/arm32_binaries.dl

@@ -75,7 +75,7 @@ direct_jump(EA,Dest):-
 direct_call(EA,Dest):-
     arch.call(EA,Index),
     instruction_get_op(EA,Index,Op),
-    op_immediate(Op,Dest0),
+    op_immediate(Op,Dest0,_),
     !instruction_has_relocation(EA,_),
     instruction_get_operation(EA,Operation),
     (
@@ -116,7 +116,7 @@ Either movw r, #N or movt r, #N
 movw_movt(EA,Reg,Val,Operation):-
     instruction(EA,_,_,Operation,ImmOp,RegOp,0,_,_,_),
     op_regdirect_contains_reg(RegOp,Reg),
-    op_immediate(ImmOp,Val),
+    op_immediate(ImmOp,Val,_),
     (Operation = "MOVW"; Operation = "MOVT").
 
 /**
@@ -267,7 +267,7 @@ may_have_symbolic_immediate(Src,Dest):-
          Operation != "MOVT",
          instruction_immediate_offset(Src,Index,_,_),
          instruction_get_op(Src,Index,Op),
-         op_immediate(Op,Imm),
+         op_immediate(Op,Imm,_),
          Dest = as(Imm,address)
          ;
          movw_movt_pair(Src,_,Value),

src/datalog/arch/arm32_symbolization.dl

@@ -297,9 +297,8 @@ litpool_symbolic_operand(LitPoolAddr2,DataAccessSize,Symbol1,Symbol2,EA_D,Reg3,S
     arch.load_operation(Operation),
     instruction_get_src_op(EA_D,_,IndOp),
     instruction_get_dest_op(EA_D,_,RegOp),
-    op_indirect_mapped(IndOp,"NONE",Reg1,Reg2,_,0,Bits),
+    op_indirect_mapped(IndOp,"NONE",Reg1,Reg2,_,0,SymSize),
     op_regdirect_contains_reg(RegOp,Reg3),
-    SymSize = Bits / 8,
 
     reg_def_use.def_used(EA_B,Reg2,EA_D,_),
 
@@ -413,7 +412,7 @@ inferred_arch_info("Profile","System"):-
     substr(Operation,0,3) = "BLX",
     arch.jump_operation_op_index(Operation,OpIndex),
     instruction_get_op(EA,OpIndex,Op),
-    op_immediate(Op,_).
+    op_immediate(Op,_,_).
 
 // ARM code is not possible on the "Microcontroller" profile.
 inferred_arch_info("Profile","System"):-

src/datalog/arch/arm64/arch_arm64.dl

@@ -124,7 +124,7 @@ data_access_size(Operation,as(DestReg,register),Size):-
 reg_arithmetic_operation(EA,Dst,Src,1,Immediate):-
     instruction(EA,_,_,"ADD",Op1,Op2,Op3,0,_,_),
     op_regdirect_contains_reg(Op1,Src),
-    op_immediate(Op2,Immediate),
+    op_immediate(Op2,Immediate,_),
     op_regdirect_contains_reg(Op3,Dst).
 
 // ADD reg, reg, reg
@@ -155,7 +155,7 @@ adr_dest(EA,Reg,as(Dest,address)):-
     // e.g. adrp x0, ImmOp
     instruction(EA,_,_,Operation,ImmOp,RegOp,0,0,_,_),
     substr(Operation,0,3) = "ADR",
-    op_immediate(ImmOp,Dest),
+    op_immediate(ImmOp,Dest,_),
     op_regdirect_contains_reg(RegOp,Reg).
 
 // mark adrp instructions as PC-relative

src/datalog/arch/arm64/memory_access.dl

@@ -40,7 +40,7 @@ reg_arithmetic_operation(EA,BaseReg_nn,BaseReg_nn,1,Offset):-
     ),
     op_indirect_mapped(Op1,"NONE",BaseReg,"NONE",_,0,_),
     reg_nonnull(BaseReg,BaseReg_nn),
-    op_immediate(Op2,Offset),
+    op_immediate(Op2,Offset,_),
     op_regdirect_contains_reg(Op3,DirectReg).
 
 // immediate - pre-index / writeback
@@ -78,7 +78,7 @@ memory_access(AccessType,EA,SrcIndex,DstIndex,DirectReg,BaseReg,"NONE",0,Offset)
 memory_access("LOAD",EA,1,2,DstReg,"NONE","NONE",0,Immediate):-
     instruction(EA,_,_,Operation,Op1,Op2,0,0,_,_),
     load_operation(Operation),
-    op_immediate(Op1,Immediate),
+    op_immediate(Op1,Immediate,_),
     op_regdirect_contains_reg(Op2,DstReg).
 
 // LDR (register)
@@ -99,7 +99,7 @@ memory_access(AccessType,EA,SrcIndex,DstIndex,DirectReg,BaseReg,IndexReg,Mult,0)
 // LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>
 // STP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>
 memory_access(AccessType,EA,SrcIndex1,DstIndex1,DirectReg1,BaseReg,"NONE",0,0),
-memory_access(AccessType,EA,SrcIndex2,DstIndex2,DirectReg2,BaseReg,"NONE",0,as(SizeBits/8,number)),
+memory_access(AccessType,EA,SrcIndex2,DstIndex2,DirectReg2,BaseReg,"NONE",0,as(SizeBytes,number)),
 reg_arithmetic_operation(EA,BaseReg_nn,BaseReg_nn,1,Offset):-
     instruction(EA,_,_,Operation,Op1,Op2,Op3,Op4,_,_),
     instruction_writeback(EA),
@@ -113,15 +113,15 @@ reg_arithmetic_operation(EA,BaseReg_nn,BaseReg_nn,1,Offset):-
     op_regdirect_contains_reg(Op1,DirectReg2),
     op_indirect_mapped(Op2,"NONE",BaseReg,"NONE",_,0,_),
     reg_nonnull(BaseReg,BaseReg_nn),
-    op_immediate(Op3,Offset),
+    op_immediate(Op3,Offset,_),
     op_regdirect_contains_reg(Op4,DirectReg1),
-    register_size_bits(DirectReg2_unmapped,SizeBits).
+    register_size_bytes(DirectReg2_unmapped,SizeBytes).
 
 // pair pre-index
 // LDP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]! (pre-index)
 // STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!
 memory_access(AccessType,EA,SrcIndex1,DstIndex1,DirectReg1,BaseReg,"NONE",0,Offset),
-memory_access(AccessType,EA,SrcIndex2,DstIndex2,DirectReg2,BaseReg,"NONE",0,Offset+as(SizeBits/8,number)),
+memory_access(AccessType,EA,SrcIndex2,DstIndex2,DirectReg2,BaseReg,"NONE",0,Offset+as(SizeBytes,number)),
 reg_arithmetic_operation(EA,BaseReg_nn,BaseReg_nn,1,Offset):-
     instruction(EA,_,_,Operation,Op1,Op2,Op3,0,_,_),
     instruction_writeback(EA),
@@ -136,13 +136,13 @@ reg_arithmetic_operation(EA,BaseReg_nn,BaseReg_nn,1,Offset):-
     op_indirect_mapped(Op2,"NONE",BaseReg,"NONE",_,Offset,_),
     reg_nonnull(BaseReg,BaseReg_nn),
     op_regdirect_contains_reg(Op3,DirectReg1),
-    register_size_bits(DirectReg2_unmapped,SizeBits).
+    register_size_bytes(DirectReg2_unmapped,SizeBytes).
 
 // pair (no writeback)
 // LDP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
 // STP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
 memory_access(AccessType,EA,SrcIndex1,DstIndex1,DirectReg1,BaseReg,"NONE",0,Offset),
-memory_access(AccessType,EA,SrcIndex2,DstIndex2,DirectReg2,BaseReg,"NONE",0,Offset+as(SizeBits/8,number)):-
+memory_access(AccessType,EA,SrcIndex2,DstIndex2,DirectReg2,BaseReg,"NONE",0,Offset+as(SizeBytes,number)):-
     instruction(EA,_,_,Operation,Op1,Op2,Op3,0,_,_),
     !instruction_writeback(EA),
     (
@@ -156,4 +156,4 @@ memory_access(AccessType,EA,SrcIndex2,DstIndex2,DirectReg2,BaseReg,"NONE",0,Offs
     op_indirect_mapped(Op2,"NONE",BaseReg,"NONE",_,Offset,_),
     reg_nonnull(BaseReg,_),
     op_regdirect_contains_reg(Op3,DirectReg1),
-    register_size_bits(DirectReg2_unmapped,SizeBits).
+    register_size_bytes(DirectReg2_unmapped,SizeBytes).

src/datalog/arch/arm64/registers.dl

@@ -26,20 +26,20 @@ This module establishes basic information about register:
  - Whether they all callee or caller saved according to the ABI
 */
 
-register_size_bits(Reg32, 32),
-register_size_bits(Reg64, 64),
+register_size_bytes(Reg32, 4),
+register_size_bytes(Reg64, 8),
 reg_map_rule(Reg32, Reg64),
 general_purpose_reg(Reg64):-
     I = range(0,29),
     Reg32 = cat("W", to_string(I)),
     Reg64 = cat("X", to_string(I)).
 
-register_size_bits("W29", 32).
-register_size_bits("W30", 32).
-register_size_bits("WSP", 32).
-register_size_bits("FP", 64).
-register_size_bits("LR", 64).
-register_size_bits("SP", 64).
+register_size_bytes("W29", 4).
+register_size_bytes("W30", 4).
+register_size_bytes("WSP", 4).
+register_size_bytes("FP", 8).
+register_size_bytes("LR", 8).
+register_size_bytes("SP", 8).
 
 reg_map_rule("W29", "FP").
 reg_map_rule("W30", "LR").

src/datalog/arch/arm64_symbolization.dl

@@ -41,7 +41,7 @@ split_load(EA, NextEA, as(Base + Offset,address), "ADD") :-
     instruction_get_operation(EA,ADROperation),
     substr(ADROperation,0,3) = "ADR",
     instruction_get_op(EA, 1, BaseOp),
-    op_immediate(BaseOp, Base),
+    op_immediate(BaseOp, Base,_),
     instruction_get_op(EA, 2, RegOp),
     op_regdirect_contains_reg(RegOp,Reg),
 
@@ -60,7 +60,7 @@ split_load(EA, NextEA, as(Base + Offset,address), "ADD") :-
     // e.g. add x0, x0, <OffsetOp>
     instruction_get_operation(NextEA, "ADD"),
     instruction_get_op(NextEA, 2, OffsetOp),
-    op_immediate(OffsetOp, Offset),
+    op_immediate(OffsetOp, Offset,_),
     instruction_get_op(NextEA, 1, RegOp2),
     op_regdirect_contains_reg(RegOp2,Reg2),
     // Make sure the registers match
@@ -76,7 +76,7 @@ split_load(EA, NextEA, as(Base + Offset,address), "LDR/STR") :-
     instruction_get_operation(EA,ADROperation),
     substr(ADROperation,0,3) = "ADR",
     instruction_get_op(EA, 1, BaseOp),
-    op_immediate(BaseOp, Base),
+    op_immediate(BaseOp, Base,_),
     instruction_get_op(EA, 2, RegOp),
     op_regdirect_contains_reg(RegOp,Reg),
 
@@ -176,8 +176,8 @@ split_load_tail(EA,Offset,Reg_nn,Type):-
     // The memory access cannot be a post-index operation. There should be no
     // immediate operand.
     instruction(EA,_,_,_,_,Op2,Op3,_,_,_),
-    !op_immediate(Op2,_),
-    !op_immediate(Op3,_),
+    !op_immediate(Op2,_,_),
+    !op_immediate(Op3,_,_),
     reg_nonnull(Reg,Reg_nn),
     Type = "LDR/STR".
 
@@ -286,7 +286,7 @@ value_reg(EA,Reg,EA,"NONE",0,Val,1):-
     track_register(Reg),
     instruction_get_op(EA,OpIndex,Op1),
     op_indirect(Op1,_,_,_,_,_,DataSize),
-    data_word(RefAddr,DataSize/8,Val).
+    data_word(RefAddr,DataSize,Val).
 
 symbolic_operand_candidate(EA,1,Dest,Type):-
     // ADR <Register> <Immediate>
@@ -299,7 +299,7 @@ symbolic_operand_candidate(EA,1,Dest,Type):-
     ),
     !split_load_operand(EA,1,_),
     instruction_get_op(EA, 1, OffsetOp),
-    op_immediate(OffsetOp, Offset),
+    op_immediate(OffsetOp, Offset,_),
     Dest = as(Offset,address),
     (
         code(Dest), Type="code"

src/datalog/arch/arm_binaries.dl

@@ -114,7 +114,7 @@ symbolic_operand_point(EA,2,-2,"arm: add r, r, n"):-
     ),
     op_regdirect_contains_reg(Op1,Reg),
     !arch.pc_reg(Reg),
-    op_immediate(Op2,_),
+    op_immediate(Op2,_,_),
     Op3 != 0,
     !symbolic_operand_attribute(EA,_,_).
 

src/datalog/arch/intel/arch_x86.dl

@@ -141,13 +141,13 @@ data_access_size("LEA",as(DestReg,register),0):-
 // ADD reg, imm
 reg_arithmetic_operation(EA,Reg,Reg,1,Immediate):-
     instruction(EA,_,_,"ADD",Op1,Op2,0,0,_,_),
-    op_immediate(Op1,Immediate),
+    op_immediate(Op1,Immediate,_),
     op_regdirect_contains_reg(Op2,Reg).
 
 // SUB reg, imm
 reg_arithmetic_operation(EA,Reg,Reg,1,-Immediate):-
     instruction(EA,_,_,"SUB",Op1,Op2,0,0,_,_),
-    op_immediate(Op1,Immediate),
+    op_immediate(Op1,Immediate,_),
     op_regdirect_contains_reg(Op2,Reg).
 
 // INC reg
@@ -163,19 +163,19 @@ reg_arithmetic_operation(EA,Reg,Reg,1,-1):-
 //shl reg immediate
 reg_arithmetic_operation(EA,Reg,Reg,2^Shift,0):-
     instruction(EA,_,_,"SHL",Op1,Op2,0,0,_,_),
-    op_immediate(Op1,Shift),
+    op_immediate(Op1,Shift,_),
     op_regdirect_contains_reg(Op2,Reg).
 
 //mul reg immediate
 reg_arithmetic_operation(EA,Reg,Reg,Mult,0):-
     instruction(EA,_,_,"IMUL",Op1,Op2,0,0,_,_),
-    op_immediate(Op1,Mult),
+    op_immediate(Op1,Mult,_),
     op_regdirect_contains_reg(Op2,Reg).
 
 //mul reg reg immediate
 reg_arithmetic_operation(EA,Dst,Src,Mult,0):-
     instruction(EA,_,_,"IMUL",Op1,Op2,Op3,0,_,_),
-    op_immediate(Op2,Mult),
+    op_immediate(Op2,Mult,_),
     op_regdirect_contains_reg(Op3,Dst),
     op_regdirect_contains_reg(Op1,Src).
 
@@ -211,7 +211,7 @@ reg_reg_arithmetic_operation(EA,Reg_def,Reg1_nn,Reg2_nn,Mult,Offset):-
     reg_nonnull(Reg1,Reg1_nn),
     reg_nonnull(Reg2,Reg2_nn).
 
-extend_reg(EA,SrcMapped,Signed,SrcBits):-
+extend_reg(EA,SrcMapped,Signed,8*SrcBytes):-
     instruction(EA,_,_,Operation,Op1,_,0,0,_,_),
     (
         Operation = "MOVZX", Signed = 0;
@@ -220,7 +220,7 @@ extend_reg(EA,SrcMapped,Signed,SrcBits):-
     ),
     move_operation(Operation),
     op_regdirect(Op1,Src),
-    register_size_bits(Src,SrcBits),
+    register_size_bytes(Src,SrcBytes),
     reg_map(Src,SrcMapped).
 
 extend_load(EA,Signed,8*SizeAccess):-