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Supported MIPS instructions
Pavel I. Kryukov edited this page Mar 18, 2019
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31 revisions
Unfortunately, MIPT-MIPS supports reduced subset of MIPS instructions at the moment.
The list of unsupported instructions goes first as it may be more important. If instruction is not listed as supported or unsupported, it is not supported.
CP0 (#588)
sdbbp
mtc0
mfc0
eret
MIPS IV Prefetches (#235)
pref
cache
sync
synci
MIPS II conditional traps (#130)
These instructions don't cause actual traps now, they print a message to the screen
teq
teqi
tge
tgei
tgeiu
tgeu
tlt
tlti
tltiu
tltu
tne
tnei
MIPS II likely branches (#91)
These branches operate as usual branches, but they don't provide any hint to BPU
beql
bgezl
bgezall
bgtzl
blezl
bltzl
bltzall
bnel
No atomicity warranty provided
ll
sc
add
addi
addiu
addu
and
andi
beq
bgez
bgezal
bgtz
blez
bltz
bltzal
bne
break
clo
clz
dadd
daddi
daddiu
daddu
dclo
dclz
ddiv
ddivu
div
divu
dmult
dmultu
dsll
dsllv
dsll32
dsra
dsra32
dsrav
dsrl
dsrl32
dsrlv
dsub
dsubu
j
jal
jalr
jr
lb
lbu
ld
ldl
ldr
lld
lh
lhu
lui
lw
lwl
lwr
lwu
madd
maddu
mfhi
mflo
movn
movz
msub
msubu
mthi
mtlo
mul
mult
multu
nor
or
ori
sb
scd
sd
sh
sdl
sdr
sll
sllv
slt
slti
sltiu
sltu
sra
srav
srl
srlv
sub
subu
sw
swl
swr
syscall
xor
xori
MIPT-V / MIPT-MIPS — Cycle-accurate pre-silicon simulation.