Update DMC to latest tapeout code

[dpetrisko]

This is the version of the DMC which was taped out in TSMC28. Main features from the previous code:

• Dly line is handled internally with a synthesizable variant
• Tag configuration is done internally and standardized to a tag structure
• Added TCALR parameter which allows for period read refreshes to tune the delay line
• Added trace replay capability for bringup of device

[dpetrisko]

Supercedes #506 #508 #535 #543

[dpetrisko]

#387 and #522 are still relevant

[akashnt4]

@taylor-bsg , @gaozihou ,
The PR is rebased and is on top of master. Simulation is clean and a brief look at the waves looked fine. Request to review and let me know in case of any questions. Thanks!

[dpetrisko]

Thanks @akashnt4! I'll take look again as well

[akashnt4]

Update : #387 is redundant and required changes are updated here.

[akashnt4]

Update after some review edits.

[gaozihou]

This counter underflows in simulation.. Maybe we could increase the max value and add an offset to the init value?

[akashnt4]

please let me know if the changed vals are okay

[gaozihou]

I guess ui_transaction_in_progress_o is broken?

Also I'd suggest not modifying the cmd_sfifo_depth_p parameter value, it would be better if we could update counter's parameter .max_val_p(2*cmd_sfifo_depth_p)

[akashnt4]

sorry, had misunderstood the comment. updated now.

[gaozihou]

Original testbench only run burst read / write. In order to test intermittent incoming command / data flits, we may add the following lines:

`ifndef CMD_GAP_CYCLES
  `define CMD_GAP_CYCLES 0
`endif

`ifndef WRITE_GAP_CYCLES
  `define WRITE_GAP_CYCLES 0
`endif

For ui_write:

  begin
    for(i=0;i<ui_burst_length_lp;i++) begin
      app_wdf_wren <= 1'b1;
      app_wdf_data <= wdata >> (ui_data_width_p * i);
      app_wdf_mask <= wmask >> (ui_mask_width_lp * i);
      if(i==ui_burst_length_lp-1) app_wdf_end <= 1'b1;
      do @(posedge ui_clk); while(!app_wdf_rdy);
      app_wdf_wren <= 1'b0;
      app_wdf_end <= 1'b0;
      repeat(`WRITE_GAP_CYCLES) @(posedge ui_clk);
    end
  end

For ui_cmd:

  begin
    app_en <= 1'b1;
    app_addr <= addr;
    app_cmd <= cmd;
    do @(posedge ui_clk); while(!app_rdy);
    app_en <= 1'b0;
    repeat(`CMD_GAP_CYCLES) @(posedge ui_clk);
  end

Similar to the frequency sweep, we may add different gap cycle options to the Makefile and test them automatically.

[akashnt4]

As the FPGA clock is going to be always slower than DMC clock, is this not happening already?

[akashnt4]

based on slack chat, add this infra here as we don't know when the UVM testbench will be mainline.

[dpetrisko]

Hi @gaozihou , is this good to go / what would be needed to get this merged?

[dpetrisko]

Just rebased by the way!