Removed all synopsys translate_off/on pragmas #689
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Seems reasonable to me. @taylor-bsg I would suggest to future-proof we use: ifndef BSG_HIDE_FROM_SYNTHESIS where in bsg_defines.sv ifdef SYNTHESIS Which will let us have per-tool logic in the future if we need to |
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@sifferman thanks for your contribution Ethan. Would you be able to modify the pull request as suggested by @dpetrisko? @dpetrisko would you be able to verify that BP and bsg_manycore are cool with this? |
sifferman
commented
Aug 31, 2024
| @@ -74,6 +74,7 @@ module bsg_mem_2rw_sync_mask_write_bit_synth #( parameter `BSG_INV_PARAM(width_p | |||
| else | |||
| b_addr_r <= 'X; | |||
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| `ifndef BSG_HIDE_FROM_SYNTHESIS | |||
There was a problem hiding this comment.
I saw that this file was missing the ifndef SYNTHESIS, so I added it
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Just made the changes! |
taylor-bsg
approved these changes
Sep 3, 2024
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TY! |
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Thanks! |
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Hello!
According to the IEEE 1364.1-2005 spec 6.3.2, the use of
translate_off/translate_onis discouraged as opposed to`ifndef SYNTHESIS. Plus, some newer SystemVerilog frontends such as sv2v, Verible, and PySlint do not have any extra AST support fortranslate_off, so they may get confused by unsupported unsynthesizable constructs.Therefore, I changed 200 occurrences of
translate_offto`ifndef SYNTHESIS.I would be happy to hear another perspective if you feel that
translate_offis in fact the better option.Thanks!