Language Conversion Brainstorm

General principles

While creating the intermediate representation we focused on meeting 3 guiding principles.

Generic, Versatile, Compatible

Generic: The intermediate representation aims to represent all netlists. New features that existing parsers and composers aren't expected to handle shouldn't be added. Constructs that are specific to a single language can probably be recreated using existing features. One such example is the verilog assignment statement which could be bypassed entirely by careful naming, or it could be worked around by creating an assignment logic block which is implemented using a new definition and instances of that definition.

Versatile: We wanted the intermediate representation to fulfill a variety of needs for constructs in all languages. Some things may need to be added for a particular composer and parser. If possible the parser and composer of that construct should be designed to handle new constructs. Metadata dictionaries are useful for this. The EDIF format, as created by Xilinx Vivado, has a rename property used to maintain names which would not be valid. Since this information is not important structural information, SpyDrNet uses the metadata dictionary to hold the information needed to maintain the renaming structure through the SpyDrNet. This information can be safely ignored when writing to another format because the real, complex name is used in the name field. When the information is not present, rename fields can easily be generated in the composer when they are not present.

Compatible: SpyDrNet was intended to be compatible with a variety of netlist structures. To maintain this compatibility when parsing a new language think of how the constructs might be represented in a different language. This can help to maintain compatility with other languages.

Verilog to EDIF

EDIF Composer:

• Make sure the can handle multi bit cables and ports
• Ensure this can handle the verilog namespace

Verilog Parser:

• Make a new element that is an assign element
• Apply the new assign element for the port remapping function

EDIF to Verilog

EDIF Parser:

• Make sure this create mutli bit cables and ports
• use the complex name instead of the rename by default
  • https://www.xilinx.com/support/answers/1554.html
  • http://electrosofts.com/verilog/identifiers.html#:~:text=An%20identifier%20is%20any%20sequence,are%20considered%20to%20be%20different.

Verilog Composer:

• Make it deal with the new assign element
• make it undo the new assign element to a port remapping where applicable (optional, probably won't implement)
• Do something meaningful with EDIF rename