This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
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Updated
Aug 12, 2017 - Verilog
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools
16-bit MIPS processor implemented in Verilog (as a part of Computer Organisation course)
A Verilog based Fractal Set Generator for the Xilinx Artix 7
FPGA Tetris written in Verilog
An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.
Design of a system bus architecture - Team Project @ ENTC UoM
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The Repository contains the code of various Digital Circuits
A single cycle CPU running MIPS instructions on Xilinx FPGA
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To implement the elevator controller, we used Verilog as HDL. The focus of our project was the implementation and verification of a controller for a basic elevator functionality. We also proposed a methodology that utilizes the SCAN algorithm to enhance the efficiency and reliability of the controller.
UART implementation using Verilog HDL
RISC22 is a simple 22-bit RISC CPU designed in VHDL, featuring a minimal instruction set and a pipelined architecture for efficient execution.
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